1. Field of the Invention
This invention relates to a digital switching unit for use in a multirate time-division multiplex digital switching network and more particularly, to a network wherein time-multiplexed data derived from time multiplexing of component data having different rates are interleaved with other time-multiplexed data. 2. Description of the Prior Art
The time-multiplexed data are trnasmitted to the switching unit via two-way second-order trunks, e.g. at the 64 kbit/s digital rate. These time-multiplexed data arised from time-multiplexing of component data as octets present a multiframe of 80 octets as defined in draft Recommendation X.50 of the International Telephone and Telegraph Consultative Committee. A time multiplexed data transmitting on a line of a trunk at 64 kbit/s can be formed by multiplexing of first-order lines or channels transmitting component data at different low rates of 12.8, 8.4, 3.2 and 0.8 kbit/s, this multiplexing being achieved by recurrent octets.
Each octet of a first-order channel comprises 6 information bits, a bit F reserved for multiplexed framing purposes, i.e. for recovering the rank of the octet in the 80-octet multiframe and a status bit S of the first-order channel to which said octet belongs. Consequently, the binary flow rates of the component low rate data are respectively 12.8, 6.4, 3.2 and 0.8 kbit/s when the binary flow rates for the user are 9.6, 4.8, 2.4 and 0.6 kbit/s, respectively.
The switching network transmits the incoming second-order channels which are given a second time multiplexing converting them into 8 parallel third-order multiplex lines, each having a 1 Mbit/s rate if the switching unit is connected to 128 second-order trunks.
U.S. Pat. No. 3,987,251 likewise describes time-division multiplexing of first-order digital channels converting them into second-order digital channels wherein component data transmitted by first-order channels have different rates. A 80-octet multiframe of a second-order multiplex channel at 64 kbit/s comprises at the same time recurrent octets at a rate one octet repeated every five octets for a 12.8 kbit/s component channel, one octet repeated every twenty octets for a 3.2 kbit/s component channel, or one octet repeated every eighty octets for a 0.8 kbit/s component channel, for example.
In the switching unit of a multirate multiplex digital switching network, each octet of the different second-order channels must be written into a buffer store at an address depending on the address of the first-order component channel in the 80-octet multiframe of the second-order channel. However, in such units the address of the first-order channel does not depend in a simple fashion on the address of the octet in the multiframe transmitted on third-order multiplex. The octet address is associated with the first-order channel adress determined by the multiplexing shemes of said second-order channels.
In this end, in accordance with the U.S. Pat. No. 3,987,251, a read-only memory is used for addressing in writing-in and reading-out the buffer store which receives and transmits the octets. This read-only memory is addressed by the whole addresses of the octets, i.e. by fourteen-bits addresses for 128 second-order channels, and provides at its output the addresses of the first-order component channels. According to this U.S. Patent, an octet address consists of two parts. A first address part determines the octet rank in the third-order multiframe or the address of the corresponding second-order channel and comprises seven bits as there are 128 second-order channels. The second address part defines the time-slot allocated to the octet of the 80-octet multiframe corresponding to said second-order channel and may include up to seven bits. In fact, the number of bits necessary to write such a second address part depends on the number of time-slots in the multiframe and requires 3, 5 or 7 bits if the 64 kbit/s second-order channel is derived from time-division multiplexing of 5, 20 or 80 component first-order channels. Such a switching unit therefore requires a read-only memory capable of storing the addresses of all the octets of each second-order multiframe. Thus such a switching unit adapted to treat 128 second-order channels or trunk lines requires the storage of 128.times.80.times.7=71 680 bits.